1. Field of the Invention
The present invention relates to an analog-to-digital (AD) conversion circuit and an imaging apparatus having the same.
Priority is claimed on Japanese Patent Application No. 2011-132196, filed Jun. 14, 2011, the content of which is incorporated herein by reference.
2. Description of Related Art
As examples using an AD conversion circuit of the related art, configurations disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-347931 and Takayuki Toyama et al., “A 17.7 Mpixel 120 fps CMOS Image Sensor with 34.8 Gb/s Readout,” Sony, Kanagawa, Japan ISSCC2011/SESSION23/IMAGE SENSORS/23.11 are well known. First, a configuration and operation of the AD conversion circuit according to the example of the related art will be described.
FIG. 26 shows a configuration of a (complementary) metal oxide semiconductor ((C)MOS) imaging apparatus using an AD conversion circuit according to the related art. The imaging apparatus 1001 shown in FIG. 26 includes an imaging section 1002, a vertical selection section 1012, a read current source section 1005, an analog section 1006, a count section 1018, a ramp section 1019, a column processing section 1015, a horizontal selection section 1014, an output section 1017, and a control section 1020.
The control section 1020 controls parts such as the vertical selection section 1012, the read current source section 1005, the analog section 1006, the count section 1018, the ramp section 1019, the column processing section 1015, the horizontal selection section 1014, and the output section 1017. The imaging section 1002 is configured to include unit pixels 1003 having photoelectric conversion elements arranged in a matrix, to generate a pixel signal corresponding to the amount of an incident electromagnetic wave, and to output the generated pixel signal to a vertical signal line 1013 provided for every column.
The vertical selection section 1012 controls row addressing or row scanning of the imaging section 1002 via a row control line 1011 when each unit pixel 1003 of the imaging section 1002 is driven. The horizontal selection section 1014 controls column addressing or column scanning of a column AD conversion section 1016 of the column processing section 1015. The read current source section 1005 is a current source for reading a pixel signal from the imaging section 1002 as a voltage signal. The analog section 1006 performs amplification or the like, if necessary.
The column processing section 1015 includes the column AD conversion section 1016 configured of a comparison section 1109 and a latch section 1108 for each column of the unit pixels 1003. The column AD conversion section 1016 converts an analog signal, which is a pixel signal output from each unit pixel 1003 of the imaging section 1002 for each column, into digital data, and outputs the digital data. The count section 1018 counts a clock signal output from the control section 1020 as a count clock, and outputs a digital (binary) value indicating a count result.
The digital value output from the count section 1018 is input to the ramp section 1019. The ramp section 1019 generates a ramp wave that changes along a gradient with the passage of time according to the input digital value, and outputs the ramp wave as a reference signal to one of input terminals of the comparison section 1109. An output of the count section 1018 is distributed to the latch section 1108 of each column. A pixel signal is input as an analog signal to be subjected to AD conversion from the unit pixel 1003 to the other of the input terminals of the comparison section 1109 within each column AD conversion section 1016 via the vertical signal line 1013.
The horizontal selection section 1014 controls column addressing or column scanning of each column AD conversion section 1016 in the column processing section 1015. Thereby, digital data subjected to AD conversion is sequentially output to the output section 1017 via a horizontal signal line.
Next, an AD conversion operation according to the related art will be described. First, in synchronization with a clock signal input from the control section 1020, the ramp section 1019 starts the generation of a ramp wave simultaneously when the count section 1018 starts a count operation. A signal read from the unit pixel 1003 of each column and a common ramp wave of which the amplitude changes in synchronization with a count value of the count section 1018 are input to the comparison section 1109 of each column. In parallel with this, the count value of the count section 1018 is distributed to the latch section 1108.
If the magnitude relationship between two input signals for the comparison section 1109 of a certain column becomes reversed, a comparison output of the comparison section 1109 is inverted and the latch section 1108 of the column retains a count value of the count section 1018. According to the above operation, a signal read from a pixel is AD-converted into a value (digital value) retained in the latch section 1108.
Although the description of a specific operation of the unit pixel is omitted here, a reset level and a signal level are output from the unit pixel as is well known. In order to accurately acquire a digital value of a signal component (a signal for a difference between the reset level and the signal level), it is necessary to carry out a subtraction operation (correlated double sampling (CDS) process) on the reset level and the signal level in a digital region. To obtain a digital value of a signal component in the configuration of the example of the related art, after digital values of the reset level and the signal level have been retained in the latch section 1108 within the column section (column AD conversion section 1016) corresponding to each column of the unit pixels 1003, the subtraction operation (CDS process) on digital values of the reset level and the signal level is performed using an arithmetic device provided outside the column section.
Here, an imager for use in a digital still camera (DSC) or the like is considered as an example of a specific device. Specifically, specs in which the number of pixels is 2000 104 and a frame rate is 60 frames/sec are assumed. Assuming that a pixel array of 2000 104 pixels is designated as 4000 rows 5000 columns in length and width in order to facilitate description and a blanking period is absent for further simplicity, the number of rows from which pixel signals are read per second is as follows.60 frames/sec 4000 rows/frame=240K lines/sec
That is, a read rate of one row becomes 240 KHz (about 4.2 sec). If a pixel signal is output via an output signal line of one system, the read rate is as follows.240K lines/sec 5000 columns=1.2 GHz
That is, the data rate becomes about 1.2 GHz (about 0.8 nsec). In this calculation, because reading from optical black (OB) pixels or other dummy pixels is excluded, reading is actually performed only at a higher frequency than a frequency estimated as described above.